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    A Breker Seminar Series

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    Portable Stimulus Live!

Portable Stimulus Live!

Accelerating and Simplifying Your Verification Using the New Standard

A Breker Seminar Series

Advanced testbench synthesis that leverages the new Accellera Portable Stimulus Standard (PSS) offers significant benefits for UVM block-based, SoC software driven and post-silicon verification. Verification schedules are dramatically reduced while effectiveness and coverage may be increased.

This free, half-day seminar, including lunch, will provide everything you need to know about PSS and how to make use of it. We will provide an overview of the language itself, and how it improves existing environments. We will explore two case studies with real examples to demonstrate how it works in practical environments, before examining strategic situations where PSS can make a difference.

Advanced Testbench Synthesis with Portable Stimulus

Location

Radisson Blu Bengaluru
0-4 Marathahalli/Outer Ring Road
Bangalore, Karnataka, India 560037
Map

Hotel Lobby

Agenda

Portable Stimulus Logo9:00 – 9:30: Arrival

9:30 – 9:45: Welcome and Introduction

9:45 – 10:15: Next-Generation Verification Based On Portable Stimulus
David Kelf
We will provide an overview of PSS test synthesis and how is fits into existing environments. We will discuss how abstracting test scenarios can improve UVM and SoC verification, eliminating a lot of painful coding.

10:15 – 11:00: The Accellera Portable Stimulus Standard (PSS) Language Basics
Harish Yagain
We will provide a detailed overview of the PSS language using the Willamette-HDL PSS training course introduction. This professional training overview gives a clear perspective on PSS and scenario description.

11:00 – 11:15: Break

11:15 – 12:00: Portable Stimulus Applied to UVM Block and SoC Verification Case Studies
David Kelf
Leading from the language overview, we will now explain how UVM and SoC environments can be updated with PSS. Synthesize complex UVM multi-threaded, synchronized sequence sets, together with scoreboards and coverage. Generate C-tests and transactions for SoC verification that uncover complex corner-case issues from a functional specification description.

12:00 – 12:30: Strategic Developments with Portable Stimulus
David Kelf
PSS Test Synthesis opens up a number of strategic opportunities, previously difficult to accomplish. Automated RISC-V and ARM processor platform testing, automotive ISO 26262 test generation and coverage, and advanced security testing are examples of advanced verification topics to be covered.

12:30-2:00: Lunch

Registration

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