9:00 – 9:30: Arrival
9:30 – 9:45: Welcome and Introduction
9:45 – 10:15: Next-Generation Verification Based On Portable Stimulus
We will provide an overview of PSS test synthesis and how is fits into existing environments. We will discuss how abstracting test scenarios can improve UVM and SoC verification, eliminating a lot of painful coding.
10:15 – 11:00: The Accellera Portable Stimulus Standard (PSS) Language Basics
We will provide a detailed overview of the PSS language using the Willamette-HDL PSS training course introduction. This professional training overview gives a clear perspective on PSS and scenario description.
11:00 – 11:15: Break
11:15 – 12:00: Portable Stimulus Applied to UVM Block and SoC Verification Case Studies
Leading from the language overview, we will now explain how UVM and SoC environments can be updated with PSS. Synthesize complex UVM multi-threaded, synchronized sequence sets, together with scoreboards and coverage. Generate C-tests and transactions for SoC verification that uncover complex corner-case issues from a functional specification description.
12:00 – 12:30: Strategic Developments with Portable Stimulus
PSS Test Synthesis opens up a number of strategic opportunities, previously difficult to accomplish. Automated RISC-V and ARM processor platform testing, automotive ISO 26262 test generation and coverage, and advanced security testing are examples of advanced verification topics to be covered.
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